Bruno has 21 years experience in the semi-conductor industry and over 17 years of senior leadership experience in early stage companies including 12 years focusing on imaging and printing market.

Prior to joining Scaleo chip, Bruno hold the position of President of TAK Imaging France, COO and founder of TAK Imaging group, a Silicon Valley based emerging growth company providing complete system solutions to the consumer photo inkjet and dye sublimation printer markets, for which he help raised in excess of $40M in series A, B and C of Venture Capital money. TAK Imaging was sold to InSilica in August 2007.

After obtaining a Masters degree in Electrical Engineering in 1986, Bruno Paucard started his career as Engineer at INRIA, a French research center in computer technology, before joining GIPSI in 1989 as ASIC Leader. He funded TAK’ASIC, an ASIC design house boutique, in 1991, that he transformed into a printing technology product company in 2000, and flipped to a US entity in 2003. TAK’ASIC changed name in 2004 to become TAK Imaging.

Pascal Jullien has been in charge of the Advanced Technology Management since January 2008, after 3 years spent to manage the R&D Department in Scaleo chip.

In 1996 he participated to the creation of Europe Technologies, named today Scaleo chip, and put in place the SoC design activity and software development. He is one of the creator of the FCM® platform concept.

After receiving his Electronic Engineering degree with speciality in micro-electronics at Montpellier University in 1989, Pascal Jullien joined Sorep SA for 5 years to develop ASICs for wireless (Alcatel), flight simulator (Dassault Avionic), satellite (Matra Marconi Space) and others applications. In 1995, he joined Texas Instruments as ARM Project Leader to develop chips for DECT application.

Bernard Plessier joined Scaleo chip as the VP of Research & Development in charge of all hardware and software product development.

Dr. Bernard Plessier received a B.S and M.S degrees in electrical engineering from the ENSPM in Marseille, France in 1988 and a Ph.D. degree in electrical engineering from the University of Colorado in 1993.

From 1993 to 1996, he was a technical staff at Motorola SPS where he developed formal verification tools. At the end of 1996, he joined STMicroelectronics as Chief Architect for cryptographic co-processors within the smartcard organization.

In 2001, he was appointed Manager of the smartcard design center in Singapore and in 2005, he came back to France as Senior Design Manager for the wireless infrastructure division of STM in charge of ASSP and ASIC product development for this division.

Prior to joining Scaleo chip, Laurent Gay, a 20+ years veteran in the ASIC and electronics industry, was Global Account Director at Elcoteq, where he developed a worldwide business with a major European Telecom company.

Previously Laurent was Europe Executive Sales Manager at Coventor where he promoted MEMS design tools and methodologies to large semiconductor firms, including STMicroelectronics. Before joining Coventor, he was South Europe Director at Radysys, a custom embedded computer boards manufacturer, where he established a regional sales office and successfully developed the business with major Telecom and Industrial companies.

Upon completion of an MS degree in Electronics from ENSEA, Laurent started his career pioneering the ASIC technology in the 80.s with various support, marketing and sales positions at RCA / GE. He recently received an MBA from IAE Paris.

Vincent has a degree in information technology from university of Paul Sabatier in Toulouse , France. Afterwards, he specialized in production & quality management.

Before joining Scaleo chip, Vincent spent 11 years with Motorola / Freescale Semiconductor Company in Automotive semiconductor manufacturing.

He was part of the fab industrial engineering staff and then took manufacturing manager position in the 6' smartmos semiconductor line.

In 2004, he joined the 300mm Crolles II R&D alliance center in France with ST microelectronique, NXP and TSMC. He led internal & external new product introduction qualification in probe pilot line for wireless & consumer Freescale products in CMOS 90nm up to 65 nm.

Noel Stasiaczyk is a graduate of the Business School of Tours (Finance Department).

Before joining Scaleo chip, Noel spent 8 years in Finance Department and International Development.

Previously, he was Audit Manager for PriceWaterhouse Coopers.